1. Field of the Invention
The present invention relates to a liquid crystal panel and a fabrication method thereof, and more particularly, to a liquid crystal panel and a fabrication method thereof for preventing an image quality of a liquid crystal panel from being degraded by suppressing an afterimage and a flicker.
2. Description of the Related Art
FIG. 1 is a plan view of an In-Plane switching mode liquid crystal panel according to the related art, and FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1.
Referring to FIGS. 1 and 2, a liquid crystal panel includes a thin film transistor 28 disposed at a crossing of a gate line 12 and a data line 22, a plurality of pixel electrodes 33 connected to a drain electrode 25 of the TFT electrode, and a common electrode 17 crossly formed to be separated from the pixel electrode 33 at a predetermined distance. A storage capacitor Cst 27 is formed at a region where the common line 15 and the drain electrode 25 are overlapped.
The TFT 28 includes a gate electrode 13 connected to the gate line 12, a source electrode 23 connected to the data line 22, a drain electrode 25 connected to the pixel electrode 33 through a contact hole 31 and a semiconductor layer 21 for forming a channel between the source electrode 23 and the drain electrode 25 by a gate voltage supplied from the gate electrode 13. The semiconductor layer 21 is formed by sequentially stacking an active layer 21a and an ohmic contact layer 21b. 
The TFT 28 further includes a gate insulating layer 19 for insulating the gate electrode 13 from the source and drain electrode 23 and 25. The TFT 28 transfers a data signal from the data line 22 to the pixel electrode 33 in response to a gate signal from the gate line 12.
The pixel electrode 33 is arranged on a cell region defined by the data line 22 and the gate line 12 and is made of a transparent conductive material such as indium tin oxide (ITO). The pixel electrode 33 is formed on a passivation layer 29 that is formed on the entire surface of the board 11, and is electrically connected to the drain electrode 25 through the contact hole 31 penetrating through the passivation layer 29.
In the cell region, a common electrode 17 is parallel and interlaced with the pixel electrode at a predetermined interval. The common electrode 17 may be formed of a material identical to the gate electrode 13 or to the pixel electrode 33.
The storage capacitor Cst 27 is provided at a region where the common line 15 and the drain electrode 25 are overlapped with the gate insulating layer 19 interposed therebetween.
A parasitic capacitor Cgd 26 is provided at a region where the gate electrode 13 and the drain electrode 25 are overlapped with a gate insulating layer 19 interposed therebetween. Although it is not shown in the accompanying drawings, a parasitic capacitor Cgs is provided at a region where the gate electrode 13 and the source electrode 23 are overlapped, and another parasitic capacitor Cds is provided between the source electrode 23 and the drain electrode 25. Herein, the capacitance of the parasitic capacities Cgs and Cds are very small compared to the capacitance of the parasitic capacitor Cgd 26.
Herein, a region A in FIG. 1 is a design margin region of the parasitic capacitor Cgd 26 for twisting of a top and bottom overlay because the design margin region depends on a width and a length of a channel.
FIG. 3 shows an equivalent circuit diagram of a pixel unit of the liquid crystal panel of FIG. 1. As shown in FIG. 1, the gate electrode 13, the source electrode 23 and the drain electrode 25 of the TFT 28 are connected to the gate line 12, the data line 22 and the pixel electrode 33, respectively. In FIG. 3, a liquid crystal capacitor Clc is generated by a liquid crystal material filled between the pixel electrode 33 and the common electrode 17. The storage capacitor Cst 27 is formed at a region where the gate electrode 13 and the drain electrode 25 are overlapped. The parasitic capacitor Cgd 26 is provided at a region where the gate electrode 13 and the drain electrode 25 are overlapped with the gate insulating layer 19 interposed therebetween. In addition, the parasitic capacitor Cgs is provided at a region where the gate electrode 13 and the source electrode 23 are overlapped with the gate insulating layer 19 interposed therebetween. Furthermore, another parasitic capacitor Cds is provided at a region where the source electrode 23 and the drain electrode 25 are overlapped with the gate insulating layer 19 interposed therebetween.
Hereinafter, the operations of the liquid crystal panel according to the related art will be described.
At first, a gate-on voltage is supplied to the gate electrode 13 connected to a target gate line 12 turns on the TFT 28, and a data voltage Vd+, i.e., the data signal, is supplied to the drain electrode 25 by supplying the data voltage Vd+ to the source electrode 23. Then, the data voltage Vd+ is supplied to the liquid crystal capacitor Clc and the storage capacitor Cst 27 through the pixel electrode 33. As a result, an electric field is generated by a potential difference between the pixel electrode 33 and the common electrode 17. Since the liquid crystal is deteriorated if an electric field with same directivity is continuously supplied to the liquid crystal, the data signal is supplied with the polarity thereof repeatedly changing from a plus polarity (+) to a minus polarity (−) or vice versa against a common voltage Vcom.
The voltage, which is supplied to the liquid crystal capacitor Clc and the storage capacitor Cst 27 when the TFT 28 is turned on, must be maintained constantly even when the TFT 28 is turned off. However, the voltage supplied to the pixel electrode 33 is distorted due to the parasitic capacitor Cgd 36 between the gate electrode 13 and the drain electrode 25. Such a distorted voltage is called a kick-back voltage. The kick-back voltage is expressed as the following Eq. 1.
                              Δ          ⁢                                          ⁢                      V            p                          =                                            C              gd                                                      C                gd                            +                              C                st                            +                              C                lc                                              ⁢          Δ          ⁢                                          ⁢                      V            g                                              Eq        .                                  ⁢        1            
In Eq. 1, Cgd denotes a parasitic capacitor between the gate electrode and the drain electrode, Cst denotes a sub capacitor, Clc denotes a liquid crystal capacitor and ΔVg denotes a variation of the gate voltage (Vgon-Voff).
Such a voltage distortion always pulls down the voltage of the pixel electrode 33 regardless of the polarity of the data voltage as shown in FIG. 4.
In an ideal liquid crystal panel, the data voltage is constantly maintained even when the gate voltage Vg becomes OFF as shown in a dotted line of FIG. 4. However, in a real liquid crystal panel, the pixel voltage Vp is reduced by the amount of the kick-back voltage ΔVp, as shown in a solid line of FIG. 4, due to the kick-back voltage ΔVp when the gate voltage Vg transits from a high state to a low state.
In order to improve the image quality by reducing the afterimages or flickers, the kickback voltage ΔVp must be identical throughout all cells in the panel or among frames.
To keep kickback voltage ΔVp identical throughout all cells, the parasitic capacitor Cgd at each cell has to uniform in order to constantly maintain the kick-back voltage ΔVp in all cells.
However, it is very difficult to optimize a design of a liquid crystal panel to uniformly maintain the parasitic capacitor Cgd 26 at each cell. If the drain electrode 25 is slightly shifted in the up or down direction due to misalignment at the small design margin region A, it will increase a deviation of the parasitic capacitor Cgd 26. Such a changing of the deviation makes the kick-back voltage ΔVp varied.
Since it is difficult to control the kick-back voltage ΔVp, when the parasitic capacitor Cgd 26 cannot be uniformly maintained throughout the entire liquid crystal panel, the image quality of the liquid crystal panel is degraded due to the afterimages and the flickers which are caused by the deviation of the kick-back voltage.